An SOC Foundry Proof Point with Demonstrated Customer Success

In this paper, we present a concrete proof point, achieved after roughly two years of collaborative effort, resulting in substantially decreased time-to-silicon and improved semiconductor customer success. We describe a foundry package containing a unique Cadence evaluation test chip, available today, and fabricated using the 0.18um CMOS Tower Semiconductor process design kit, Tower standard-cells, Tower memories, and Tower IO libraries. This unique IC design entity is specifically architected so as to quickly enable complete analog, mixed-signal, digital, memory, and IO design styles to be immediately exercised by semiconductor houses without expending additional resources developing and testing their own comprehensive reduced-risk enterprise-wide flow environment. The authors strive to outline this example of close mutual cooperation toward an innovative goal between the foundry, the EDA software supplier, and the multi-domain semiconductor designer as a seminal proof point for the industry as a whole.